Finfet device with a substantially self-aligned isolation region positioned under the channel region

ABSTRACT

One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure generally relates to the fabrication ofintegrated circuits, and, more particularly, to various embodiments of aFinFET device with a substantially self-aligned isolation regionpositioned under the channel region of the device.

2. Description of the Related Art

In modern integrated circuits, such as microprocessors, storage devicesand the like, a very large number of circuit elements, especiallytransistors, are provided and operated on a restricted chip area.Immense progress has been made over recent decades with respect toincreased performance and reduced feature sizes of circuit elements,such as transistors. However, the ongoing demand for enhancedfunctionality of electronic devices forces semiconductor manufacturersto steadily reduce the dimensions of the circuit elements and toincrease the operating speed of the circuit elements. The continuingscaling of feature sizes, however, involves great efforts in redesigningprocess techniques and developing new process strategies and tools so asto comply with new design rules. Generally, in complex circuitryincluding complex logic portions, MOS technology is presently apreferred manufacturing technique in view of device performance and/orpower consumption and/or cost efficiency. In integrated circuitsincluding logic portions fabricated by MOS technology, field effecttransistors (FETs) are provided that are typically operated in aswitched mode, that is, these devices exhibit a highly conductive state(on-state) and a high impedance state (off-state). The state of thefield effect transistor is controlled by a gate electrode, whichcontrols, upon application of an appropriate control voltage, theconductivity of a channel region formed between a drain region and asource region.

To improve the operating speed of FETs, and to increase the density ofFETs on an integrated circuit device, device designers have greatlyreduced the physical size of FETs over the years. More specifically, thechannel length of FETs has been significantly decreased, which hasresulted in improving the switching speed of FETs. However, decreasingthe channel length of a FET also decreases the distance between thesource region and the drain region. In some cases, this decrease in theseparation between the source and the drain makes it difficult toefficiently inhibit the electrical potential of the source region andthe channel from being adversely affected by the electrical potential ofthe drain. This is sometimes referred to as a so-called short channeleffect, wherein the characteristic of the FET as an active switch isdegraded.

In contrast to a FET, which has a planar structure, a so-called FinFETdevice has a three-dimensional (3D) structure. FIG. 1A is a perspectiveview of an illustrative prior art FinFET semiconductor device “A” thatis formed above a semiconductor substrate B that will be referenced soas to explain, at a very high level, some basic features of a FinFETdevice. In this example, the FinFET device A includes three illustrativefins C, a gate structure D, sidewall spacers E and a gate cap layer F.The gate structure D is typically comprised of a layer of gateinsulating material (not separately shown), e.g., a layer of high-kinsulating material or silicon dioxide, and one or more conductivematerial layers (e.g., metal and/or polysilicon) that serve as the gateelectrode for the device A. The fins C have a three-dimensionalconfiguration: a height H, a width W and an axial length L. The axiallength L corresponds to the direction of current travel in the device Awhen it is operational. The portions of the fins C covered by the gatestructure D are the channel regions of the FinFET device A. In aconventional process flow, the portions of the fins C that arepositioned outside of the spacers E, i.e., in the source/drain regionsof the device A, may be increased in size or even merged together (asituation not shown in FIG. 1A) by performing one or more epitaxialgrowth processes. The process of increasing the size of or merging thefins C in the source/drain regions of the device A is performed toreduce the resistance of source/drain regions and/or make it easier toestablish electrical contact to the source/drain regions. Even if an epi“merger” process is not performed, an epi growth process will typicallybe performed on the fins C to increase their physical size.

In the FinFET device A, the gate structure D may enclose both sides andthe upper surface of all or a portion of the fins C to form a tri-gatestructure so as to use a channel having a three-dimensional structureinstead of a planar structure. In some cases, an insulating cap layer(not shown), e.g., silicon nitride, is positioned at the top of the finsC and the FinFET device only has a dual-gate structure (sidewalls only).Unlike a planar FET, in a FinFET device, a channel is formedperpendicular to a surface of the semiconducting substrate so as toreduce the physical size of the semiconductor device. Also, in a FinFET,the junction capacitance at the drain region of the device is greatlyreduced, which tends to significantly reduce short channel effects. Whenan appropriate voltage is applied to the gate electrode of a FinFETdevice, the surfaces (and the inner portion near the surface) of thefins C, i.e., the vertically oriented sidewalls and the top uppersurface of the fin, form a surface inversion layer or a volume inversionlayer that contributes to current conduction. In a FinFET device, the“channel-width” is estimated to be about two times (2×) the verticalfin-height plus the width of the top surface of the fin, i.e., the finwidth. Multiple fins can be formed in the same foot-print as that of aplanar transistor device. Accordingly, for a given plot space (orfoot-print), FinFETs tend to be able to generate significantly higherdrive current density than planar transistor devices. Additionally, theleakage current of FinFET devices after the device is turned “OFF” issignificantly reduced as compared to the leakage current of planar FETs,due to the superior gate electrostatic control of the “fin” channel onFinFET devices. In short, the 3D structure of a FinFET device is asuperior MOSFET structure as compared to that of a planar FET,especially in the 20 nm CMOS technology node and beyond. The gatestructures D for such FinFET devices may be manufactured using so-called“gate-first” or “replacement gate” (gate-last) manufacturing techniques.

For many early device technology generations, the gate structures ofmost transistor elements (planar or FinFET devices) were comprised of aplurality of silicon-based materials, such as a silicon dioxide and/orsilicon oxynitride gate insulation layer, in combination with apolysilicon gate electrode. However, as the channel length ofaggressively scaled transistor elements has become increasingly smaller,many newer generation devices employ gate structures that containalternative materials in an effort to avoid the short channel effectswhich may be associated with the use of traditional silicon-basedmaterials in reduced channel length transistors. For example, in someaggressively scaled transistor elements, which may have channel lengthson the order of approximately 10-32 nm or less, gate structures thatinclude a so-called high-k dielectric gate insulation layer and one ormore metal layers that function as the gate electrode (HK/MG) have beenimplemented. Such alternative gate structures have been shown to providesignificantly enhanced operational characteristics over the heretoforemore traditional silicon dioxide/polysilicon gate structureconfigurations.

Depending on the specific overall device requirements, several differenthigh-k materials—i.e., materials having a dielectric constant, ork-value, of approximately 10 or greater—have been used with varyingdegrees of success for the gate insulation layer in an HK/MG gateelectrode structure. For example, in some transistor element designs, ahigh-k gate insulation layer may include tantalum oxide (Ta₂O₅), hafniumoxide (HfO₂), zirconium oxide (ZrO₂), titanium oxide (TiO₂), aluminumoxide (Al₂O₃), hafnium silicates (HfSiO_(x)) and the like. Furthermore,one or more non-polysilicon metal gate electrode materials—i.e., a metalgate stack—may be used in HK/MG configurations so as to control the workfunction of the transistor. These metal gate electrode materials mayinclude, for example, one or more layers of titanium (Ti), titaniumnitride (TiN), titanium-aluminum (TiAl), titanium-aluminum-carbon(TiALC), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalumnitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN),tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.

One well-known processing method that has been used for forming atransistor with a high-k/metal gate structure is the so-called “gatelast” or “replacement gate” technique. The replacement gate process maybe used when forming planar devices or 3D devices. FIGS. 1B-1Esimplistically depict one illustrative prior art method for forming anHK/MG replacement gate structure using a replacement gate technique on aplanar transistor device. As shown in FIG. 1B, the process includes theformation of a basic transistor structure above a semiconductingsubstrate 12 in an active area defined by a shallow trench isolationstructure 13. At the point of fabrication depicted in FIG. 1A, thedevice 10 includes a sacrificial gate insulation layer 14, a dummy orsacrificial gate electrode 15, sidewall spacers 16, a layer ofinsulating material 17 and source/drain regions 18 formed in thesubstrate 12. The various components and structures of the device 10 maybe formed using a variety of different materials and by performing avariety of known techniques. For example, the sacrificial gateinsulation layer 14 may be comprised of silicon dioxide, the sacrificialgate electrode 15 may be comprised of polysilicon, the sidewall spacers16 may be comprised of silicon nitride and the layer of insulatingmaterial 17 may be comprised of silicon dioxide. The source/drainregions 18 may be comprised of implanted dopant materials (N-typedopants for NMOS devices and P-type dopants for PMOS devices) that areimplanted into the substrate 12 using known masking and ion implantationtechniques. Of course, those skilled in the art will recognize thatthere are other features of the transistor 10 that are not depicted inthe drawings for purposes of clarity. For example, so-called haloimplant regions are not depicted in the drawings, as well as variouslayers or regions of silicon/germanium that are typically found in highperformance PMOS transistors. At the point of fabrication depicted inFIG. 1B, the various structures of the device 10 have been formed and achemical mechanical polishing (CMP) process has been performed to removeany materials above the sacrificial gate electrode 15 (such as aprotective cap layer (not shown) comprised of silicon nitride) so thatat least the sacrificial gate electrode 15 may be removed.

As shown in FIG. 1C, one or more etching processes are performed toremove the sacrificial gate electrode 15 and the sacrificial gateinsulation layer 14 to thereby define a gate cavity 20 where areplacement gate structure will subsequently be formed. Typically, thesacrificial gate insulation layer 14 is removed as part of thereplacement gate technique, as depicted herein. However, the sacrificialgate insulation layer 14 may not be removed in all applications.

Next, as shown in FIG. 1D, various layers of material that willconstitute a replacement gate structure 30 are formed in the gate cavity20. Even in cases where the sacrificial gate insulation layer 14 isintentionally removed, there will typically be a very thin native oxidelayer (not shown) that forms on the substrate 12 within the gate cavity20. The materials used for the replacement gate structures 30 for NMOSand PMOS devices are typically different. For example, the replacementgate structure 30 for an NMOS device may be comprised of a high-k gateinsulation layer 30A, such as hafnium oxide, having a thickness ofapproximately 2 nm, a first metal layer 30B (e.g., a layer of titaniumnitride with a thickness of about 1-2 nm), a second metal layer 30C—aso-called work function adjusting metal layer for the NMOS device—(e.g.,a layer of titanium-aluminum or titanium-aluminum-carbon with athickness of about 5 nm), a third metal layer 30D (e.g., a layer oftitanium nitride with a thickness of about 1-2 nm) and a bulk metallayer 30E, such as aluminum or tungsten.

Ultimately, as shown in FIG. 1E, one or more CMP processes are performedto remove excess portions of the gate insulation layer 30A, the firstmetal layer 30B, the second metal layer 30C, the third metal layer 30Dand the bulk metal layer 30E positioned outside of the gate cavity 20 tothereby define the replacement gate structure 30 for an illustrativeNMOS device. Typically, the replacement metal gate structure 30 for aPMOS device does not include as many metal layers as does an NMOSdevice. For example, the gate structure 30 for a PMOS device may onlyinclude the high-k gate insulation layer 30A, a single layer of titaniumnitride—the work function adjusting metal for the PMOS device—having athickness of about 3-4 nm, and the bulk metal layer 30E.

FIG. 1F depicts the device 10 after several process operations wereperformed. First, one or more etching processes were performed to removeupper portions of the various materials within the cavity 20 so as toform a recess within the gate cavity 20. Then, a gate cap layer 31 wasformed in the recess above the recessed gate materials. The gate caplayer 31 is typically comprised of silicon nitride and it may be formedby depositing a layer of gate cap material so as to over-fill the recessformed in the gate cavity and thereafter performing a CMP process toremove excess portions of the gate cap material layer positioned abovethe surface of the layer of insulating material 17. The gate cap layer31 is formed so as to protect the underlying gate materials duringsubsequent processing operations.

One problem that is encountered in forming FinFET devices relates topreventing leakage currents underneath the fin structures. This issometimes referred to as so-called “punch through” leakage currents. Oneprior art effort to eliminate or reduce such undesirable punch throughleakage currents involved forming counter-doped regions that werepositioned at approximately the intersection between the fin and theremaining portion of the substrate. However, obtaining an accuratedoping profile that is properly positioned underneath the active FIN isvery difficult to accomplish, especially given that the additionalthermal heating processes that are involved in subsequent process stepswill further drive dopant diffusion and make it harder to control thelocation of the anti-punch-through doping. If dopant diffuses into theFINs during subsequent annealing processes, it would cause thresholdvoltage fluctuation because of the random amount of the dopant diffusedinto FINs of different devices, which would severely compromise thecircuit performance. Additionally, fabrication of FinFET devices mayinvolve formation of stressed layers of insulation material in an effortto induce a desired stress on the channel region of the FinFET device,e.g., a tensile stress for N-type FinFET devices and a compressivestress for P-type FinFET devices. Such stressed channel regions areformed in an effort to improve the electrical performancecharacteristics of the N-type and P-type FinFET devices. Thus, an effortat reducing the undesirable punch through leakage currents must notunduly detract from the benefits achieved by virtue of the formation ofthe stressed materials that induce the desired stress in the channelregion of the FinFET devices.

The present disclosure is directed to various methods of formingsubstantially self-aligned isolation regions on FinFET semiconductordevices, and the resulting semiconductor devices, that may avoid, or atleast reduce, the effects of one or more of the problems identifiedabove.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the present disclosure is directed to various methods offorming substantially self-aligned isolation regions on FinFETsemiconductor devices, and the resulting semiconductor devices. Onemethod disclosed includes, among other things, forming a first layer ofa first semiconductor material on a semiconductor substrate, forming asecond layer of a second semiconductor material on the first layer ofthe first semiconductor material, wherein the first layer of the firstsemiconductor material is selectively etchable relative to thesemiconductor substrate and the second layer of the second semiconductormaterial, forming a plurality of spaced-apart trenches that extend atleast partially into the semiconductor substrate, wherein the trenchesdefine a fin structure comprised of the first and second layers ofsemiconductor material, and forming a sacrificial gate structure above aportion of the fin structure at a location that correspondsapproximately to a location of the channel region for the device. Inthis example, the method further includes forming at least one sidewallspacer adjacent the sacrificial gate structure, performing at least oneetching process to remove the sacrificial gate structure and therebydefine a gate cavity, while masking portions of the fin structurepositioned outside of the spacers, performing at least one selectiveetching process through the gate cavity to selectively remove a portionof the first layer of the first semiconductor material relative to thesecond layer of the second semiconductor material and the substrate soas to thereby define a space between the second semiconductor materialand the semiconductor substrate, filling substantially all of the spacebetween the second semiconductor material and the semiconductorsubstrate with an insulating material so as to thereby define asubstantially self-aligned channel isolation region positioned under atleast what will become the channel region of the device and, afterforming the substantially self-aligned channel isolation region, forminga final gate structure in the gate cavity.

Another illustrative method disclosed herein includes, among otherthings, forming a first layer of a first semiconductor material on asemiconductor substrate, forming a second layer of a secondsemiconductor material on the first layer of the first semiconductormaterial, wherein the first layer of the first semiconductor material isselectively etchable relative to the semiconductor substrate and thesecond layer of the second semiconductor material, forming a pluralityof spaced-apart trenches that extend at least partially into thesemiconductor substrate, wherein the trenches define a fin structure forthe device comprised of the first and second layers of semiconductormaterial, and forming a patterned layer of insulating material above thefin structure, wherein the patterned layer of insulating material has anopening at a location that corresponds approximately to a location ofthe channel region for the device. In this example, the method alsoincludes, while masking portions of the fin structure with the patternedlayer of insulating material, performing at least one selective etchingprocess through the opening in the patterned layer of insulatingmaterial to selectively remove a portion of the first layer of the firstsemiconductor material relative to the second layer of the secondsemiconductor material and the substrate so as to thereby define a spacebetween the second semiconductor material and the semiconductorsubstrate, filling substantially all of the space between the secondsemiconductor material and the semiconductor substrate with aninsulating material so as to thereby define a substantially self-alignedchannel isolation region positioned under at least what will become thechannel region of the device, forming a sacrificial gate structurewithin the opening in the patterned layer of insulating material,removing the patterned layer of insulating material, forming at leastone sidewall spacer adjacent the sacrificial gate structure, forming alayer of insulating material adjacent the sidewall spacer, performing atleast one etching process to remove the sacrificial gate structure tothereby define a gate cavity, and forming a final gate structure in thegate cavity.

One illustrative device disclosed herein includes, among other things, asemiconductor substrate, a fin structure that is positioned verticallyabove the substrate, the fin structure being comprised of a firstsemiconductor material, a gate structure positioned around a portion ofthe fin structure in the channel region of the device, spaced-apartportions of a second semiconductor material positioned verticallybetween the fin structure and the substrate, wherein the secondsemiconductor material is a different semiconductor material than thefirst semiconductor material, and a local channel isolation materialpositioned laterally between the spaced-apart portions of the secondsemiconductor material and vertically below the fin structure and thegate structure, wherein the local channel isolation material ispositioned under at least a portion of the channel region of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIG. 1A is a perspective view of one illustrative embodiment of a priorart FinFET device;

FIGS. 1B-1F depict one illustrative prior art method of forming a gatestructure using a so-called “replacement gate” technique;

FIGS. 2A-2H depict one illustrative method disclosed for formingsubstantially self-aligned isolation regions on FinFET semiconductordevices, and the resulting semiconductor devices; and

FIGS. 3A-3J depict another illustrative method disclosed for formingsubstantially self-aligned isolation regions on FinFET semiconductordevices, and the resulting semiconductor devices.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below.In the interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

The present disclosure generally relates to various methods of formingsubstantially self-aligned isolation regions on FinFET semiconductordevices, and the resulting semiconductor devices. Moreover, as will bereadily apparent to those skilled in the art upon a complete reading ofthe present application, the present method is applicable to a varietyof devices, including, but not limited to, logic devices, memorydevices, etc., and the methods disclosed herein may be employed to formN-type or P-type semiconductor devices. The methods and devicesdisclosed herein may be employed in manufacturing products using avariety of technologies, e.g., NMOS, PMOS, CMOS, etc., and they may beemployed in manufacturing a variety of different devices, e.g., memorydevices, logic devices, ASICs, etc. As will be appreciated by thoseskilled in the art after a complete reading of the present application,the inventions disclosed herein may be employed in forming integratedcircuit products using a variety of so-called 3D devices, such asFinFETs. For purposes of disclosure, reference will be made to anillustrative process flow wherein a single FinFET device 100 is formed.Moreover, the inventions will be disclosed in the context of forming thegate structures using a replacement gate (“gate-last”) processingtechnique. Of course, the inventions disclosed herein should not beconsidered to be limited to the illustrative examples depicted anddescribed herein. With reference to the attached figures, variousillustrative embodiments of the methods and devices disclosed hereinwill now be described in more detail.

FIGS. 2A-2H depict one illustrative method disclosed for formingsubstantially self-aligned isolation regions on FinFET semiconductordevices, and the resulting semiconductor devices. The illustrativedevice 100 will be formed in and above the semiconductor substrate 102.The device 100 may be either an NMOS or a PMOS transistor. Additionally,various doped regions, e.g., source/drain regions, halo implant regions,well regions and the like, are not depicted in the attached drawings.The substrate 102 may have a variety of configurations, such as thedepicted bulk silicon configuration. The substrate 102 may be made ofsilicon or it may be made of materials other than silicon. Thus, theterms “substrate” or “semiconductor substrate” should be understood tocover all semiconducting materials and all forms of such materials.

FIGS. 2A-2H present various views of one illustrative embodiment of aFinFET device 100 that may be formed using the methods disclosed herein.The drawings also include a simplistic plan view of the device 100 (inthe upper right corner) that depicts the location where variouscross-sectional views depicted in the following drawings will be taken.More specifically, the view “X-X” is taken along the axial length of thegate electrode of the device (i.e., along the gate width direction ofthe device 100), the view “Y-Y” is a cross-sectional view that is takenthrough the long axis of a fin (i.e., in the current transport directionof the device), the view “Z-Z” is a cross-sectional view that is takenthrough the source/drain region of the device in a direction that istransverse to the long axis of the fins.

FIG. 2A depicts the device 100 at a point in fabrication wherein severalprocess operations have been performed. First, a first layer of episemiconductor material 104 is deposited on the surface of thesemiconductor substrate 102. In one example, the layer of episemiconductor material 104 may be a layer of silicon germanium(Si_(x)Ge_(1-x)). The thickness of the epi semiconductor material 104may vary depending upon the particular application. In one illustrativeembodiment, the layer of epi semiconductor material 104 may have athickness of about 5-15 nm. The epi semiconductor material 104 may beformed using any of a variety of different traditional epitaxialdeposition processes. Thereafter, a second layer of epi semiconductormaterial 106 is deposited on the surface of the epi semiconductormaterial 104. In one example, the layer of epi semiconductor material106 may be a layer of silicon. The thickness of the epi semiconductormaterial 106 may vary depending upon the particular application. In oneillustrative embodiment, the layer of epi semiconductor material 106 mayhave a thickness of about 20-45 nm. The epi semiconductor material 106may be formed using any of a variety of different traditional epitaxialdeposition processes.

FIG. 2B depicts the device 100 after several process operations wereperformed. First, one or more etching processes were performed through apatterned etch mask (not shown) so as to define a plurality of trenches108 in the substrate 102. This results in the formation of a pluralityof substrate fins 110. During this process, the first layer of episemiconductor material 104 and the second layer of epi semiconductormaterial 106 were also patterned so as to result in the structuredepicted in FIG. 2B. The illustrative FinFET device 100 disclosed hereinwill be depicted as being comprised of three illustrative fins. However,as will be recognized by those skilled in the art after a completereading of the present application, the methods and devices disclosedherein may be employed when manufacturing FinFET devices having anynumber of fins. The fins 110 extend laterally in the current transportdirection and into what will become the source/drain regions of thedevice 100.

In one embodiment, the trenches 108 were formed by performing one ormore etching processes through one or more patterned etch masks (notshown), e.g., a patterned hard mask layer, using known etchingtechniques. The patterned etch masks may be patterned using knownsidewall image transfer techniques and/or photolithographic techniques,combined with performing known etching techniques. In some applications,a further etching process may be performed to reduce the width or to“thin” the fins, although such a thinning process is not depicted in theattached drawings. For purposes of this disclosure and the claims, theuse of the terms “fin” or “fins” should be understood to refer to finsthat have not been thinned as well as fins that have been subjected tosuch a thinning etch process. The device 100 may be electricallyisolated from adjacent devices by one or more isolation regions (notshown) formed in the substrate 102.

With continuing reference to FIG. 2B, the overall size, shape andconfiguration of the trenches 108 and fins 110 may vary depending on theparticular application. The depth and width of the trenches 108 may varydepending upon the particular application. In one illustrativeembodiment, based on current day technology, the depth of the trenches108 (below the upper surface 106S) may range from approximately 50-200nm and the width of the trenches 108 may be about 15-60 nm. In someembodiments, the fins 110 may have a final width (at or near the bottomof the fin) within the range of about 5-20 nm. In the illustrativeexamples depicted in the attached figures, the trenches 108 and fins 110are all of a uniform size and shape. However, such uniformity in thesize and shape of the trenches 108 and the fins 110 is not required topractice at least some aspects of the inventions disclosed herein. Inthe example depicted herein, the trenches 108 are formed by performingan anisotropic etching process that results in the trenches 108 having aschematically depicted, generally rectangular configuration. In anactual real-world device, the sidewalls of the trenches 108 may besomewhat inwardly tapered, although that configuration is not depictedin the drawings. In some cases, the trenches 108 may have a reentrantprofile near the bottom of the trenches 108. To the extent the trenches108 are formed by performing a wet etching process, the trenches 108 maytend to have a more rounded configuration or non-linear configuration ascompared to the generally rectangular configuration of the trenches 108that are formed by performing an anisotropic etching process. Thus, thesize and configuration of the trenches 108 and the fins 110, and themanner in which they are made, should not be considered a limitation ofthe present invention. For ease of disclosure, only the substantiallyrectangular trenches 108 and fins 110 will be depicted in subsequentdrawings.

Also depicted in FIG. 2B is a layer of insulating material 112, e.g.,silicon dioxide, that is formed between the fins 110 within the trenches108. The insulating material 112 may be formed so as to exhibit adesired stress (e.g., tensile or compressive) or it may be formed in asubstantially unstressed state. The layer of insulating material 112depicted in FIG. 2B may be formed using a variety of techniques. In oneillustrative process flow, the process flow for forming the layer ofinsulating material 112 includes the following steps: (1) perform theetching process(es) to etch through the first and second layers (106,104) of the epi semiconductor material so as to form the trenches 108;(2) over-fill the trenches 108 with an insulating material (stressed orunstressed), e.g., such as silicon dioxide; (3) perform a CMP process onthe layer of silicon dioxide that stops on the upper surface 106S of thefins 110; and (4) performing an etching process on the layer ofinsulating material 112 so as to recess the upper surface 112S of thelayer of insulating material 112 to a desired height level. Importantly,the layer of insulating material 112 is recessed to the point that itsupper recessed surface 112S is positioned at a level that is below alevel of the upper surface 104S of the epi semiconductor material 104.In short, the layer of insulating material 112 is recessed to such anextent that at least a portion of the epi semiconductor material 104 isexposed. In one illustrative embodiment, the layer of insulatingmaterial 112 is recessed such that its upper surface 112S is positionedat least about 5 nm below the upper surface 104S of the episemiconductor material 104.

In the example disclosed herein, the FinFET device 100 will be formedusing a replacement gate technique. Accordingly, FIG. 2C depicts thedevice 100 at a point in fabrication wherein several process operationshave been performed. More specifically, a sacrificial gate structure 120has been formed above the substrate 102 and the fins 110. Also depictedis an illustrative gate cap layer 126 and sidewall spacers 130. The gatecap layer 126 and the sidewall spacers 130 are typically made of siliconnitride. The source/drain regions for the device are formed outside ofthe spacers 130, in the region depicted in view Z-Z. The source/drainregions may be formed by performing an in-situ doped epi process or byperforming one or more conventional ion implantation processes. The epimaterial can be formed directly on the exposed fin or after the fin hasbeen recessed (not shown). The epi material can be merged or unmerged.Such additional epi material is not depicted in the source/drain regionsso as not to obscure aspects of the presently disclosed inventions. Atthis point in the replacement gate process flow, an anneal process wouldhave already been performed to activate the implanted dopant materialsand repair any damage to the substrate 102 due to the various ionimplantation processes that were performed. The sacrificial gatestructure 120 includes a sacrificial gate insulation layer 122 and adummy or sacrificial gate electrode 124. The various components andstructures of the device 100 may be formed using a variety of differentmaterials and by performing a variety of known techniques. For example,the sacrificial gate insulation layer 122 may be comprised of silicondioxide and the sacrificial gate electrode 124 may be comprised ofpolysilicon. The various layers of material depicted in FIG. 2C, as wellas the layers of material described below, may be formed by any of avariety of different known techniques, e.g., a chemical vapor deposition(CVD) process, an atomic layer deposition (ALD) process, a thermalgrowth process, spin-coating techniques, etc. Moreover, as used hereinand in the attached claims, the word “adjacent” is to be given a broadinterpretation and should be interpreted to cover situations where onefeature actually contacts another feature or is in close proximity tothat other feature.

FIG. 2D depicts the device 100 after several process operations wereperformed. First, a layer of insulating material 132 was deposited abovethe device 100 and a CMP process was then performed to planarize theupper surface of the layer of insulating material 132 with the uppersurface of the gate cap layer 126 (see FIG. 2C). Thereafter, one or morewet or dry etching processes were performed to remove the gate cap layer126, the sacrificial gate electrode 124 and the sacrificial gateinsulation layer 122 to thereby define a gate cavity 134 where areplacement gate structure will subsequently be formed for the device100.

FIG. 2E depicts the device 100 after an etching process, such as anisotropic etching process, was performed to selectively remove theportions of the epi semiconductor material 104 exposed by the gatecavity 134 relative to the substrate 102 and the epi semiconductormaterial 106. As depicted in view Z-Z, in one illustrative embodiment,the epi semiconductor material 104 positioned outside of the spacers 130(i.e., in the source/drain regions of the device 100) is protectedduring this etching process by the layer of insulating material 132, andthus is not removed. This etching process results in the formation of asubstantially self-aligned space 136 (relative to the gate cavity 134)for an isolation material to be positioned under what will become thechannel region for the device 100. In one embodiment, the space 136 hasa lateral width 136W (in the current transport or gate length direction)that is slightly larger than the lateral width 134W of the gate cavity134. As noted above, in one embodiment, the epi semiconductor material104 is not removed in areas outside of the spacers 130, i.e., thematerial 104 is not removed in the source/drain regions of the device100.

Next, as shown in FIG. 2F, a conformal deposition process was performedso as to form a layer of insulating material 140, e.g., silicon dioxideso as to substantially fill the space 136 that is substantially alignedwith the gate cavity 134. In one embodiment, this process operationinvolves depositing the layer of insulating material 140 with athickness of about half of the space 136, followed by isotropicallyetching back the layer of insulating material 140 with a target removalamount being approximately equal to the initially deposited thickness ofthe layer of insulating material 140, as described more fully below.

FIG. 2G depicts the device 100 after an etch-back process, such as anisotropic etch-back process, was performed so as to remove portions ofthe layer of insulating material 140. This etching process also removesportions of the layer of insulating material 140 from the sidewalls 106Xand upper surface 106S of the fins 110 within the gate cavity 134. Thisprocess operation results in the formation of the substantiallyself-aligned channel isolation region 140 that is positioned under atleast the channel region of the device 100. In one embodiment, thelateral width 136W (see FIG. 2E) of the channel material 140 is largerthan the lateral width of the final gate structure for the device, whichcorresponds approximately to the width 134W (see FIG. 2E) at a pointjust above the upper surface 106S of the fins 110.

Thereafter, several known processing operations were performed to form aschematically depicted replacement gate structure 150 in the gate cavity134, as depicted in FIG. 2H. The replacement gate structure 150 depictedherein is intended to be representative in nature of any type of gatestructure that may be employed in manufacturing integrated circuitproducts using so-called gate-last (replacement gate) manufacturingtechniques. The replacement gate structure 150 typically comprises ahigh-k (k value greater than 10) gate insulation layer (not individuallyshown), such as hafnium oxide, one or more metal layers (notindividually shown) (e.g., layers of titanium nitride or TiAlC dependingupon the type of transistor device being manufactured), and a bulkconductive material layer (not individually shown), such as tungsten oraluminum. Typically, the various layers of material that will be presentin the replacement gate structure 150 are sequentially deposited in thegate cavity 134 and above the layer of insulating material 132 and oneor more CMP processes are performed to remove excess portions of thegate materials positioned outside of the gate cavity 134, as describedin the background section of this application. Then, one or more etchingprocesses were performed to remove upper portions of the variousmaterials within the cavity 134 so as to form the replacement gatestructure 150 and to form a recess above the replacement gate structure150. Then, a gate cap layer 152 was formed in the recess above therecessed gate materials. The gate cap layer 152 is typically comprisedof silicon nitride and it may be formed by depositing a layer of gatecap material so as to over-fill the recess formed in the gate cavity 134above the replacement gate structure 150 and thereafter performing a CMPprocess to remove excess portions of the gate cap material layer 152positioned above the surface of the layer of insulating material 132.The gate cap layer 152 is formed so as to protect the underlying gatematerials during subsequent processing operations.

As will be appreciated by those skilled in the art after a completereading of the present application, the FinFET device 100 depicted inFIG. 2H has a unique structure and provides unique benefits relative toprior art FinFET devices. More specifically, positioning of the local,substantially self-aligned channel isolation material 140 (enclosed bydashed lines 141) under all or a substantial portion of the channelregion of the device 100 may result in better electrical performance ofthe device 100, e.g., the reduction or elimination of undesirable punchthrough currents, without causing any substantial threshold voltagefluctuation due to random dopant diffusion. As noted above, in oneembodiment, the substantially self-aligned channel isolation material140 has a lateral width (in the current transport direction) that iswider than the replacement gate structure 150 and the channel region ofthe device 100. Moreover, using the novel process flow depicted herein,the epi semiconductor material 104 may still remain positioned betweenthe substrate 102 and the epi semiconductor material 106 in thesource/drain regions laterally outside of the spacers 130 (see view Z-Zin FIG. 2H). Of course, if desired, a process flow may be adopted inwhich the epi semiconductor material 104 positioned outside of thespacers 130 is substantially consumed or replaced, e.g., by forminginverted or embedded source/drain regions for the device 100 using wellknown techniques.

FIGS. 3A-3J depict another illustrative method disclosed for formingsubstantially self-aligned isolation regions on FinFET semiconductordevices, and the resulting semiconductor device. In this embodiment,relative to the embodiment shown in FIGS. 2A-2H, the substantiallyself-aligned channel isolation region 140 is formed prior to theformation of the sacrificial gate structure 120. FIG. 3A depicts thedevice 100 at a point in fabrication that corresponds to that depictedin FIG. 2B, i.e., after the trenches 108 were formed in the substrate102 so as to define the substrate fins 110, and after the layer ofinsulating material 112 was formed between the fins 110 within thetrenches 108. Also depicted in FIG. 3A is a liner 160, such as a siliconnitride liner, and a layer of insulating material 162, such as a layerof silicon dioxide. The liner 160 may be of any desired thickness and itmay be formed by performing a conformal deposition process. The layer ofinsulating material 162 may likewise be formed to any desired thicknessand it may be formed by performing a CVD process. FIG. 3A depicts thedevice after the upper surface of the layer of insulating material 162has been planarized by performing a CMP process.

FIG. 3B depicts the device 100 after the layer of insulating material162 has been patterned to define an opening 164 above a region where thegate structure for the device 100 will ultimately be formed. The opening164 may be formed by forming a patterned etch mask (not shown), e.g., apatterned layer of photoresist, above the layer of insulating material162 and thereafter performing an anisotropic etching process using theliner layer 160 as an etch-stop layer.

FIG. 3C depicts the device 100 after an etching process was performed toremove the portions of the liner layer 162 exposed by the opening 164.This etching process exposes the upper surface 106S within the opening164.

FIG. 3D depicts the device 100 after an etching process, such as anisotropic etching process, was performed to selectively remove theportions of the epi semiconductor material 104 exposed by the gatecavity 164 relative to the substrate 102 and the epi semiconductormaterial 106. As depicted, in one illustrative embodiment, the episemiconductor material 104 positioned in the source/drain regions of thedevice 100 (see views Y-Y and Z-Z) is protected during this etchingprocess by the layer of insulating material 162, and thus is notremoved. This etching process results in the formation of asubstantially self-aligned space 136 (relative to the opening 164)positioned under what will become the channel region for the device 100.In one embodiment, the space 136 has a lateral width 136W that isslightly larger than the lateral width 164W of the opening 164. As notedabove, in one embodiment, the epi semiconductor material 104 is notremoved in the source/drain regions of the device 100.

Next, as shown in FIG. 3E, a conformal deposition process was performedso as to form the above-described layer of insulating material 140,e.g., silicon dioxide, such that it substantially fills the space 136that is substantially aligned with the opening 164. In the embodimentdepicted in FIGS. 3A-3J, the layer of insulating material 140 will alsoserve as the sacrificial gate insulation layer for the sacrificial gatestructure 120 that will be formed for the device 100. Also depicted inFIG. 3E is a layer of sacrificial gate material 166, e.g., polysilicon,that has been deposited across the device and in the opening 164. Asnoted above, the layer of insulating material 140 may be initiallydeposited with a thickness of about half of the space 136 so as toreliably fill the space 136.

FIG. 3F depicts the device 100 after one or more CMP processes have beenperformed to remove materials positioned above the upper surface of thelayer of insulating material 162.

FIG. 3G depicts the device 100 at a point in fabrication wherein severalprocess operations have been performed. First one or more etch-backprocesses were performed on the sacrificial gate material 166 such thatits upper surface 166S is recessed to make room for the depicted gatecap layer 170. The gate cap layer 170 may be formed by depositing alayer of gate cap material and thereafter performing a CMP process toremove excess materials positioned above the layer of insulatingmaterial 162.

FIG. 3H depicts the device 100 after one or more etching processes areperformed to remove the exposed portions of the layer of insulatingmaterial 140 and the layer of insulating material 162. This etchingprocess stops on the liner layer 160. As will be appreciated by thoseskilled in the art, in this embodiment, the sacrificial gate structure120 is comprised of the remaining portions of the layer of insulatingmaterial 140 and the layer of sacrificial gate material 166. Thedepicted gate cap layer 170 is positioned above the sacrificial gatestructure 120 shown in FIG. 3H.

FIG. 3I depicts the device 100 at a point in fabrication wherein severalprocess operations have been performed. More specifically, sidewallspacers 172 have been formed adjacent the sacrificial gate structure120. The sidewall spacers 172 are typically made of silicon nitride. Thespacers 172 may be formed by depositing a layer of spacer material andperforming an anisotropic etching process. In the case where the linerlayer 160 and the spacers 172 are made of the same material, the exposedportions of the liner layer 160 may also be removed when the spacers areformed. Alternatively, after the spacers 172 are formed, the exposedportions of the liner layer 160 may be removed by performing anotheretching process. Thereafter, source/drain regions for the device may beformed. However, as noted above, any epi material that may have beenformed in the source/drain regions of the device is not depicted in thedrawings.

FIG. 3J depicts the device 100 after several process operations wereperformed. First, the above-described layer of insulating material 132was formed above the device 100 and planarized so as to expose the gatecap layer 170 (see FIG. 3I). Thereafter, one or more wet or dry etchingprocesses were performed to remove the gate cap layer 170, thesacrificial gate material 166 and the layer of insulating material 140to thereby define a gate cavity 134 where the above-describedreplacement gate structure 150 and gate cap layer 152 are formed.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is, therefore, evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Note that the use of terms, such as “first,” “second,”“third” or “fourth,” to describe various processes or structures in thisspecification and in the attached claims is only used as a shorthandreference to such steps/structures and does not necessarily imply thatsuch steps/structures are performed/formed in that ordered sequence. Ofcourse, depending upon the exact claim language, an ordered sequence ofsuch processes may or may not be required. Accordingly, the protectionsought herein is as set forth in the claims below.

What is claimed:
 1. A FinFET device comprising a channel region and aplurality of source/drain regions, said device having a gate-lengthdirection that corresponds to a direction of current travel when saiddevice is operational, the device comprising: a semiconductor substrate;a fin structure that is positioned vertically above said substrate, saidfin structure being comprised of a first semiconductor material; a gatestructure positioned around a portion of said fin structure in saidchannel region of said device, said fin structure extending in saidgate-length direction across said channel region and said source/drainregions for said device; spaced-apart portions of a second semiconductormaterial positioned vertically between said fin structure and saidsubstrate, said second semiconductor material being a differentsemiconductor material than said first semiconductor material; and alocal channel isolation material positioned laterally between saidspaced-apart portions of said second semiconductor material andvertically below said fin structure and said gate structure, said localchannel isolation material being positioned under at least a portion ofsaid channel region of said device.
 2. The device of claim 1, whereinsaid semiconductor substrate and said first semiconductor material aresilicon and said second semiconductor material is silicon/germanium(Si_(x)Ge_(1-x)).
 3. The device of claim 1, wherein said semiconductorsubstrate and said first semiconductor material are comprised of thesame material.
 4. The device of claim 1, wherein said gate structurecomprises a gate insulation layer comprised of a high-k insulatingmaterial and a gate electrode comprised of at least one layer of metal.5. The device of claim 1, wherein said local channel isolation materialabuts each of said spaced-apart portions of said second semiconductormaterial.
 6. The device of claim 1, wherein said second semiconductormaterial is positioned under said fin structure in said source/drainregions of said device.
 7. The device of claim 1, wherein a lateralwidth of said local channel isolation material in said gate lengthdirection is greater than a lateral width of said gate structure at anupper surface of said fin structure.
 8. A FinFET device comprising achannel region and a plurality of source/drain regions, said devicehaving a gate-length direction that corresponds to a direction ofcurrent travel when said device is operational, said device comprising:a semiconductor substrate; a fin structure that is positioned verticallyabove said substrate, said fin structure being comprised of a firstsemiconductor material; a gate structure positioned around a portion ofsaid fin structure in said channel region of said device, said finstructure extending in said gate-length direction across said channelregion and said source/drain regions for said device; spaced-apartportions of a second semiconductor material positioned verticallybetween said fin structure and said substrate, said second semiconductormaterial being a different semiconductor material than said firstsemiconductor material; and a local channel isolation materialpositioned laterally between said spaced-apart portions of said secondsemiconductor material and vertically below said fin structure and saidgate structure, wherein a lateral width of said local channel isolationmaterial in said gate length direction is greater than a lateral widthof said gate structure at an upper surface of said fin structure andwherein said local channel isolation material abuts each of saidspaced-apart portions of said second semiconductor material.
 9. Thedevice of claim 8, wherein said semiconductor substrate and said firstsemiconductor material are comprised of the same material.
 10. Thedevice of claim 8, wherein said gate structure comprises a gateinsulation layer comprised of a high-k insulating material and a gateelectrode comprised of at least one layer of metal.
 11. The device ofclaim 8, wherein said second semiconductor material is positioned undersaid fin structure in said source/drain regions of said device.
 12. AFinFET device comprising a channel region and a plurality ofsource/drain regions, said device having a gate-length direction thatcorresponds to a direction of current travel when said device isoperational, said device comprising: a semiconductor substrate; a finstructure that is positioned vertically above said substrate, said finstructure being comprised of a first semiconductor material, whereinsaid semiconductor substrate and said first semiconductor material arecomprised of the same material; a gate structure positioned around aportion of said fin structure in said channel region of said device,said fin structure extending in said gate-length direction across saidchannel region and said source/drain regions for said device;spaced-apart portions of a second semiconductor material positionedvertically between said fin structure and said substrate in saidsource/drain regions, said second semiconductor material being adifferent semiconductor material than said first semiconductor material;and a local channel isolation material positioned laterally between saidspaced-apart portions of said second semiconductor material andvertically below said fin structure and said gate structure, wherein alateral width of said local channel isolation material in said gatelength direction is greater than a lateral width of said gate structureat an upper surface of said fin structure.
 13. The device of claim 12,wherein said gate structure comprises a gate insulation layer comprisedof a high-k insulating material and a gate electrode comprised of atleast one layer of metal.
 14. The device of claim 12, wherein said localchannel isolation material abuts each of said spaced-apart portions ofsaid second semiconductor material.